As integrated circuits become more complex, engineers and scientists look for ways to reduce the surface area required on the substrate for the integrated circuit. Reducing the size of the integrated circuit tends hold to the chip size to a reasonable level, and the device also tends to be operable at a higher speed. Unfortunately, as the size of integrated circuits is reduced, limits and constraints in regard to the proper operation of various device structures are encountered.
For example, one of the fundamental challenges for developing logic circuits is optimizing the speed of the logic device. Because the mobility of holes tends to be lower than the mobility of electrons in many semiconducting materials, the drive current of PMOS transistors tends to be commensurately lower than the drive current of a similarly sized NMOS device, when each is driven at equal supply voltage potentials. Thus, the low drive current of the PMOS device tends to be one speed limiting parameter in certain circuits, such as a logic inverter.
One method of compensating for this situation is to form larger PMOS devices, relative to the size of the NMOS devices. Thus, the larger PMOS structure has an ability to carry a commensurately larger drive current at the same supply voltage potential, because of the increased numbers of carriers. Unfortunately, addressing the problem by increasing the size of the PMOS structures is in direct opposition to the design goal of creating ever smaller integrated circuits.
Another method of compensating for the speed difference is to increase the drive current of the PMOS device by increasing the potential of the supply voltage at which it is driven, relative to that of the NMOS device. Unfortunately, it is often desirable to drive both the PMOS device and the NMOS device at the same potential. Thus, compensating for the difference in drive currents between the two structures in this manner is somewhat unsatisfactory. Further, if the higher drive potential is available on the chip, then it seems somewhat of a waste to not use it to drive the NMOS device at an even greater drive current. Therefore, providing different supply voltages to the different devices to balance the drive currents of the devices tends to be somewhat of an inelegant solution. Additionally, increasing the supply voltages may jeopardize the reliability of the devices due to hot carrier injection into the gate dielectric.
What is needed, therefore, is a structure, and a method for its formation, that can be used in PMOS and NMOS devices to achieve high drive currents and keep leakage currents low.